CompuLab IPC2 Manual do Utilizador Página 13

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CompuLab Ltd. FACE Modules HW Specifications Page 13 of 63
A34
GND
Ground connection
B34
EXT_PRSNT#
Clock Request for PCI Express 100 MHz
Clocks
A35
PCIE_TX3+
PCI Express (x1) Gen2 (up to 5Gbps)
differential transmit pair 3
B35
PCIE_RX3+
PCI Express (x1) Gen2 (up to 5Gbps)
differential receive pair 3
A36
PCIE_TX3-
B36
PCIE_RX3-
A37
PCIE_WAKE#
PCI Express Wake Event from Device to Host
B37
SPI_EXT_CNTRL
SPI interface external control signal
A38
PCIE_TX2+
PCI Express (x1) Gen2 (up to 5Gbps)
differential transmit pair 2
B38
PCIE_RX2+
PCI Express (x1) Gen2 (up to 5Gbps)
differential receive pair 2
A39
PCIE_TX2-
B39
PCIE_RX2-
A40
GND
Ground connection
B40
GND
Ground connection
A41
PCIE_TX1+
PCI Express (x1) Gen2 (up to 5Gbps)
differential transmit pair 1
B41
PCIE_RX1+
PCI Express (x1) Gen2 (up to 5Gbps)
differential receive pair 1
A42
PCIE_TX1-
B42
PCIE_RX1-
A43
PWRBTN#
System power button signal
B43
SLP#
Assert LP state S3 (sleep) active low
signal
A44
PCIE_TX0+
Host CPU PEG (x1) - PCIe Gen3 (up to 8Gbps)
differential transmit pair for external graphics
B44
PCIE_RX0+
Host CPU PEG (x1) - PCIe Gen3 (up to
8Gbps) differential receive pair for
external graphics
A45
PCIE_TX0-
B45
PCIE_RX0-
A46
RESERVED
Reserved debug signal
B46
RESERVED
Reserved debug signal
A47
VCC_12V
Main 12V power domain
B47
VCC_12V
Main 12V power domain
A48
VCC_12V
B48
VCC_12V
A49
VCC_12V
B49
VCC_12V
A50
VCC_12V
B50
VCC_12V
Notes:
1. Fit-PC3/3i features PCIe REF clock only on these signals
2. Merged with PCI Express signals to Mini PCIe card on fit-PC3/3i
3. Fit-PC3/3i support SATA3.0 with rates up to 6Gbps
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